The present invention relates to a technology of relieving a defect of a memory, and particularly to a semiconductor device capable of relieving defects at a probe test stage of the semiconductor device and after its assembly through the use of both of two types of memory elements different in element structure. The present invention also relates to a technology effective for application to a DRAM (Dynamic Random Access Memory), for example.
Unexamined Patent Publication No. Hei 8(1996)-31196 discloses defective address memory means which utilizes an element M1 and a fuse F1 in combination. Unexamined Patent Publication No. Hei 8(1996)-255498 discloses a first redundant address storage circuit 26 including a laser program circuit 40a, and a second redundant address storage circuit 28 including an electrically programmable circuit 42a. Unexamined Patent Publication No. Hei 7(1995)-326198 discloses the technology of storing a defective cell address in a second defective cell address memory 7 by electrical redundancy when a defect occurs in a first defective cell address memory 5 due to laser redundancy. Unexamined Patent Publication No. Hei 3(1991)-157897 (corresponding U.S. Pat. No. 5,233,566) discloses a fuse 5 corresponding to memory means for storing information used for substitution of an abnormal cell with another by non-electrical means, and an n channel FAMOS which is an EPROM cell transistor corresponding to means for storing information used for substitution with a redundant cell by electrical means. Unexamined Patent Publication No. Hei 1(1989)-261845 (corresponding U.S. Pat. No. 5,018,104) discloses a redundant circuit including a first switch element including a non-volatile memory cell provided with means for avoiding erasure, and a second switch element capable of being reset to a pre-switching state. Unexamined Patent Publication No. Hei 4(1992)-328398 (corresponding U.S. Pat. No. 5,319,599) discloses a redundant circuit including a first switch element comprised of a non-volatile memory cell, and a second switch element comprised of an element capable of freely writing and erasing data of an EPROM or the like. Unexamined Patent Publication No. Hei 11(1999)-16385 discloses a semiconductor memory device including a spare column (row) decoder for polysilicon, and a spare column (row) decoder for UPROM (unerasable PROM). Unexamined Patent Publication No. Hei 8(1996)-335674 discloses a method of trimming a semiconductor device wherein, of a plurality of circuits having different functions or characteristics, disposed between main lines of a semiconductor integrated circuit device, one circuit or two or more circuits are selectively connected to the main lines.
In a process for manufacturing a memory such as a DRAM or the like, defective bits have been relieved upon a wafer probe test. However, defects might take place newly in its subsequent aging or assembly process. Further, defective bits might be left because a relieving process is improper. It is necessary to allow relieving even after the assembly. Therefore, a discussion has been made of a case in which two types of fuses are mounted and an electric fuse relievable after assembly is used as one of them. As the two types of fuses, may be mentioned, a cutoff type laser fuse, an electrically programmable memory device or element (electric fuse) like an EPROM memory cell.
The present inventors have made a discussion about the mounting of electric fuses on a semiconductor device for the purpose of defect relief. According to the discussion, a by-chip occupied area based on electric fuses, latch circuits attendant on them, etc. becomes greatly larger than a by-chip occupied area based on cutoff type laser fuses, and latch circuits attendant on them. When all is comprised of the electric fuses, an area penalty excessively increases. Therefore, if logic circuit portions subsequent to latch circuits attendant on the cutoff type and electric fuses are dedicated for the respective fuses and made attendant thereon when an attempt is made to utilize the cutoff type and electric fuses in combination, it became evident that the area penalty excessively increased after all. The present inventors have found that when the cutoff type and electric fuses are utilized in combination, it is necessary to reduce a by-chip occupied area using or based on address wirings for supplying address information to the respective fuses and signal wirings for transferring the result of comparison, as small as possible.
The known reference has no described the standpoint that an increase in the by-chip occupied area at the time that both the electric and cutoff type fuses are used, is reduced to the utmost.
An object of the present invention is to reduce an increase in by-chip occupied area due to memory elements different in element or device structure as typified by electric and cutoff type fuses, as small as possible from a layout viewpoint when the memory elements are used to hold address information for relief.
Another object of the present invention is to improve the reliability of long-term data retention when an electric program holds address information for relief.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
[1] A semiconductor device has a first memory array unit in which normal memory cell are disposed, and a second memory array unit in which redundant memory cell are disposed. Address information of memory cells to be relieved in the first memory array unit are stored in a plurality of first memory elements and second memory elements different in element structure from one another. A plurality of first comparators respectively compare the address information stored in the first memory elements with signal information on an address signal wiring. A plurality of second comparators compare the address information stored in the second memory elements with signal information on the address signal wiring. A relief control circuit performs control for switching an access to the first memory array unit to an access to the second memory array unit according to the coincidence between the results of comparisons by the first and second comparators. The plurality of first memory elements and first comparators are formed in a first area along the address signal wiring, and the plurality of second memory elements and second comparators are formed in a second area adjacent to the first area.
The first memory elements are, for example, cutoff type fuses (cutoff fuse) which store information according to the presence or absence of cutoff. The second memory elements are, for example, electrically programmable non-volatile memory elements (electric fuses) which store information according to a difference in threshold voltage.
The first area and the second area are allocated along the address signal wiring and they are disposed so as to adjoin each other. Therefore, even if the memory elements different in device structure or circuit configuration are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.
As a desirable form, the address signal wiring may be shared between the first comparators and the second comparators. Since the first comparators and the second comparators may be disposed along the address signal wiring, there is no necessity to separately provide them. Sharing the address signal wiring therebetween allows restraint on an increase in by-chip occupied area.
As a desirable form, the address signal wiring may be provided so as to linearly cross over a portion where the first and second areas are adjacent to each other. If a bent portion is less reduced, then a wiring channel width for the address signal wiring can be made small correspondingly. Even from this point of view, a by-chip occupied area can be restrained from increasing.
If the semiconductor device is equipped with a circuit which generates a program voltage used for programming its threshold voltage when the second memory elements are of electric fuses, then each second memory element may be disposed so as to be closer to the program voltage generating circuit than each first memory element. A voltage wiring for transferring the program voltage to the second memory element can be shortened. Even from this point of view, a by-chip occupied area can be restrained from increasing.
Let""s assume a plurality of memory bank configurations with respect to the first memory array unit and the second memory array unit. At this time, the first memory array unit and the second memory array unit are disposed on both sides with the first and second areas interposed therebetween. In other words, memory banks are laid out on both sides with the first and second areas interposed therebetween. The second memory elements inherent in memory banks on the respective sides of the memory banks on both sides are disposed so as to be spaced in two stages in the second area in which the second memory elements like electric fuses relatively large in circuit scale are disposed. On the other hand, the first memory elements inherent in memory banks on the respective sides of the memory banks on both sides are disposed so as to be spaced in three stages in the first area in which the first memory elements like cutoff fuses relatively small in circuit scale are disposed. If the layout of the first memory elements like the cutoff fuses small in circuit scale is brought to high density in a three-stage layout, then an increase in the area occupied by the chip can be restrained even from this point of view.
When a defect corresponding to the full upper limit first takes place with respect to an upper limit relievable by a relief circuit, it is impossible to relieve a new or additional defect developed after its relief. If the first defect is less than the relievable upper limit, it is then possible to relieve the new defect developed after its relief. When consideration is given to an improvement in the efficiency of relieving processing in the former, the execution of relieving processing by the same procedure even if the first defect corresponds or uncorresponds to the full upper limit is efficient. Namely, the number of addresses storable by the first memory elements may be set equal to the upper limit of the number of relief addresses relievable by the second memory array unit. To this end, for example, at least, the number of the first memory elements is greater than that of the second memory elements, and the number of addresses storable by the first and second memory elements is set larger than an upper limit of the number of relief addresses relievable by the second memory array unit, and means which selects the result of comparisons by some first comparators and the result of comparisons by some second comparators may be provided.
[2] The second memory elements like electric fuses for holding relief address information may preferably have high reliability with respect to long-term information retention performance. Each of the second memory elements according to this viewpoint is provided with a non-volatile storage transistor device or element having a first source electrode, a first drain electrode, a floating gate electrode, and a control gate electrode and capable of having different threshold voltages; and a read transistor element having a second source electrode and a second drain electrode, having the floating gate electrode as a gate electrode, and capable of having mutual conductances different according to the threshold voltages held by the non-volatile storage transistor element, and may be configured so as to transmit a signal generated according to the mutual conductance of the read transistor element to transfer means.
When, for example, one threshold voltage of the non-volatile storage transistor element is set to a relatively high threshold voltage (threshold voltage in a write state in which electrons are injected into a floating gate, for example), and the other threshold voltage thereof is set to a low threshold voltage (threshold voltage in an erased state in which the electrons are emitted from the floating gate, for example) in the above description, the read transistor element is regarded as being kept in a cutoff state in a high threshold voltage state, whereas the read transistor element is regarded as being kept in an on state in a low threshold voltage state (the inverse thereof might naturally take place depending on a conduction type of a transistor device or element). For example, the first drain electrode and control gate electrode of the non-volatile storage transistor element are set to 0V like a circuit""s ground voltage, the first source electrode of the non-volatile storage transistor element is set to 6V, and electrons are extracted or drawn out from the floating gate electrode to the first source electrode through a tunnel current, thereby making it possible to achieve an erased state with respect to the non-volatile storage transistor element. For example, the first drain electrode and control gate electrode of the non-volatile storage transistor element are set to 5V, the first source electrode of the non-volatile storage transistor element is set to 0V like the circuit""s ground voltage, and hot electrons developed in the first drain electrode are injected into the floating gate, thereby making it possible to achieve the write state.
Since the floating gate electrode of the non-volatile storage transistor element serves as the gate electrode of the read transistor element, the read transistor element enters into a switch state or takes mutual conductance according to an electron injection state/electron emission state, in other words, a write state/erase state. The read transistor element can pass a current corresponding to it to the transfer means. It is not necessary to cause a channel current to flow through the transistor according to the threshold voltage of the non-volatile storage transistor element upon a read operation from the above description. Accordingly, the source electrode and drain electrode of the non-volatile storage transistor element may respectively be set to the circuit""s ground voltage like 0V upon the read operation. Thus, the injection of weak hot electrons does not take place at the floating gate as viewed from the first drain electrode. At this time, no tunnel current is developed either where the control gate electrode is also set to the circuit""s ground potential. Thus, it is possible to enhance long-term data retention performance and implement a reduction in read defective proportion.
Each of the electric fuses used as the second memory elements may comprise a flash memory cell having a stack structure in which floating and control gates are vertically stacked on each other. However, a manufacturing process becomes complex as compared with a CMOS process or the like. If consideration is paid to the application of the relieving means to a semiconductor device such as a DRAM or the like manufactured by the CMOS process, then the second memory elements like the electric fuses is more preferable if capable of being manufactured by either the CMOS process or a monolayer polysilicon gate process. For example, the non-volatile storage transistor element has a MIS capacitive element provided with a capacitive electrode functioning as a control gate electrode, on a first semiconductor region through a insulating layer, and a MIS transistor having a first source electrode, a first drain electrode and a gate electrode formed in a second semiconductor region. Further, the capacitive electrode may be configured so as to serve as a floating gate electrode by being commonly connected to each gate electrode.
Thus, the semiconductor device having the second memory elements like the electric fuses can be manufactured without definitely adding a new process to a normal logic circuit process or a general-purpose DRAM process or the like, like the CMOS process or the monolayer polysilicon gate process.
[3] A semiconductor device according to another aspect of the present invention includes a memory cell array having a plurality of memory cells, a first relief address storage circuit including a plurality of first memory elements each of which stores address information of a memory cell to be relieved in the memory cells, a second relief address storage circuit including a plurality of second memory elements each of which stores address information of a memory cell to be relieved in the memory cells, and an address signal wiring which commonly transmits address information to be compared with respective memory address information to the first relief address storage circuit and the second relief address storage circuit. The first memory element and the second memory element have element structures different from each other. The first relief address storage circuit is formed in a first area along the address signal wring. The second relief address storage circuit is formed in a second area adjacent to the first area.
A semiconductor device according to a further aspect of the present invention includes a memory cell array having a plurality of memory cells, some of which are used as redundant memory cells substituted for other memory cells, a first relief address storage circuit including a plurality of first memory elements each of which stores address information of a memory cell to be relieved by each redundant memory cell and a plurality of first comparators, a second relief address storage circuit including a plurality of second memory elements each of which stores address information of a memory cell to be relieved by each redundant memory cell and a plurality of second comparators, and an address signal wiring which commonly transmits address information to be compared with respective memory address information to the first relief address storage circuit and the second relief address storage circuit. The first memory element and the second memory element have element structures different from each other. The first comparator outputs a first select signal when the address information stored in each first storage element and signal information on the address signal wiring are found to coincide with each other from the result of comparison therebetween. The second comparator outputs a second select signal when the address information stored in each second storage element and signal information on the address signal wiring are found to coincide with each other from the result of comparison therebetween. The semiconductor device has a selector circuit which selects either the first select signal or the second select signal to thereby set the selected signal as a signal for providing instructions for selecting each redundant memory cell.